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d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct163 presettable synchronous 4-bit binary counter; synchronous reset for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; synchronous reset 74hc/hct163 features synchronous counting and loading two count enable inputs for n-bit cascading positive-edge triggered clock synchronous reset output capability: standard i cc category: msi general description the 74hc/hct163 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct163 are synchronous presettable binary counters which feature an internal look-ahead carry and can be used for high-speed counting. synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (cp). the outputs (q 0 to q 3 ) of the counters may be preset to a high or low level. a low level at the parallel enable input ( pe) disables the counting action and causes the data at the data inputs (d 0 to d 3 ) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for pe are met). preset takes place regardless of the levels at count enable inputs (cep and cet). for the 163 the clear function is synchronous. a low level at the master reset input ( mr) sets all four outputs of the flip-flops (q 0 to q 3 ) to low level after the next positive-going transition on the clock (cp) input (provided that the set-up and hold time requirements for mr are met). this action occurs regardless of the levels at pe, cet and cep inputs. this synchronous reset feature enables the designer to modify the maximum count with only one external nand gate. the look-ahead carry simplifies serial cascading of the counters. both count enable inputs (cep and cet) must be high to count. the cet input is fed forward to enable the terminal count output (tc). the tc output thus enabled will produce a high output pulse of a duration approximately equal to a high level output of q 0 . this pulse can be used to enable the next cascaded stage. the maximum clock frequency for the cascaded counters is determined by the cp to tc propagation delay and cep to cp set-up time, according to the following formula: f max 1 t p max () (cptotc) t su (cep to cp) + ------------------------------------------------------------------------------------------------ - = quick reference data gnd = 0 v; t amb =25 c; t r =t f =6ns symbol parameter conditions typical unit hc hct t phl / t plh propagation delay cp to q n cp to tc cet to tc c l =15pf; v cc =5v 17 21 11 20 25 14 ns ns ns f max maximum clock frequency 51 50 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 33 35 pf notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v
december 1990 3 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; synchronous reset 74hc/hct163 ordering information see 74hc/hct/hcu/hcmos logic package information . pin description pin no. symbol name and function 1 mr synchronous master reset (active low) 2 cp clock input (low-to-high, edge-triggered) 3, 4, 5, 6 d 0 to d 3 data inputs 7 cep count enable input 8 gnd ground (0 v) 9 pe parallel enable input (active low) 10 cet count enable carry input 14, 13, 12, 11 q 0 to q 3 ?ip-?op outputs 15 tc terminal count output 16 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
december 1990 4 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; synchronous reset 74hc/hct163 function table notes 1. the tc output is high when cet is high and the counter is at terminal count (hhhh). h = high voltage level h = high voltage level one set-up time prior to the low-to-high cp transition l = low voltage level i = low voltage level one set-up time prior to the low-to-high cp transition q = lower case letters indicate the state of the referenced output one set-up time prior to the low-to-high cp transition x = dont care - = low-to-high cp transition operating mode inputs outputs mr cp cep cet pe d n q n tc reset (clear) i - xxxxl l parallel load h h - - x x x x i i i h l h l (1) count h - h h h x count (1) hold (do nothing) h h x x i x x i h h x x q n q n (1) l fig.4 functional diagram.
december 1990 5 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; synchronous reset 74hc/hct163 fig.5 state diagram. fig.6 typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit.
december 1990 6 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; synchronous reset 74hc/hct163 fig.7 logic diagram.
december 1990 7 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; synchronous reset 74hc/hct163 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l =50pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay cp to q n 55 20 16 185 37 31 230 46 39 280 56 48 ns 2.0 4.5 6.0 fig.8 t phl / t plh propagation delay cp to tc 69 25 20 215 43 37 270 54 46 320 65 55 ns 2.0 4.5 6.0 fig.8 t phl / t plh propagation delay cet to tc 36 13 10 120 24 20 150 30 26 180 36 31 ns 2.0 4.5 6.0 fig.9 t thl / t tlh output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 figs 8 and 9 t w clock pulse width high or low 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.8 t su set-up time mr, d n to cp 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 figs 10 and 11 t su set-up time pe to cp 80 16 14 22 8 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.10 t su set-up time cep, cet to cp 175 35 30 58 21 17 220 44 37 265 53 45 ns 2.0 4.5 6.0 fig.12 t h hold time d n , pe, cep, cet, mr to cp 0 0 0 - 14 - 5 - 4 0 0 0 0 0 0 ns 2.0 4.5 6.0 figs 10, 11 and 12 f max maximum clock pulse frequency 5 27 32 15 46 55 4 22 26 4 18 21 mhz 2.0 4.5 6.0 fig.8
december 1990 8 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; synchronous reset 74hc/hct163 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. input unit load coefficient mr 0.95 cp 1.10 cep 0.25 d n 0.25 cet 0.75 pe 0.30
december 1990 9 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; synchronous reset 74hc/hct163 ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l =50pf symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay cp to q n 23 39 49 59 ns 4.5 fig.8 t phl / t plh propagation delay cp to tc 29 49 61 74 ns 4.5 fig.8 t phl / t plh propagation delay cet to tc 17 32 44 48 ns 4.5 fig.9 t thl / t tlh output transition time 7 15 19 22 ns 4.5 figs 8 and 9 t w clock pulse width high or low 20 6 25 30 ns 4.5 fig.8 t su set-up time mr, d n to cp 20 9 25 30 ns 4.5 figs 10 and 11 t su set-up time pe to cp 20 11 25 30 ns 4.5 fig.10 t su set-up time cep, cet to cp 40 24 50 60 ns 4.5 fig.12 t h hold time d n , pe, cep, cet, mr to cp 0 - 5 0 0 ns 4.5 figs 10, 11 and 12 f max maximum clock pulse frequency 26 45 21 17 mhz 4.5 fig.8
december 1990 10 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; synchronous reset 74hc/hct163 ac waveforms fig.8 waveforms showing the clock (cp) to outputs (q n , tc) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.9 waveforms showing the input (cet) to output (tc) propagation delays and output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.10 waveforms showing the set-up and hold times for the input (d n ) and parallel enable input ( pe). the shaded areas indicate when the input is permitted to change for predictable output performance. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v.
december 1990 11 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; synchronous reset 74hc/hct163 fig.11 waveforms showing the mr set-up and hold times. the shaded areas indicate when the input is permitted to change for predictable output performance. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.12 waveforms showing the cep and cet set-up and hold times. the shaded areas indicate when the input is permitted to change for predictable output performance. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. application information the hc/hct163 facilitate designing counters of any modulus with minimal external logic. the output is glitch-free due to the synchronous reset. fig.13 modulo-5 counter. package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.14 modulo-11 counter.

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